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Chapter 8. Advanced Experiments 8.7. Experiment with 8-bit Serial AD Converter ADC0832 The ADC0831 series are 8-bit successive approximation A/D converters with a serial I/O and configurable input multiplexers with up to 8 channels. The serial I/O is configured to comply with the NSC MICROWIRETM serial data exchange standard for easy interface to the COPSTM family of processors, and can interface with standard shift registers or mPs. The 2-, 4- or 8-channel multiplexers are software configured for single-ended or differential inputs as well as channel assignment. The differential analog voltage input allows increasing the common-mode rejection and offsetting the analog zero input voltage value. In addition, the voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of resolution. Features NSC MICROWIRE compatible - direct interface to COPS family processors Easy interface to all microprocessors, or operates stand-alone Operates ratio metrically or with 5 VDC voltage reference No zero or full-scale adjust required 2-, 4- or 8-channel multiplexer options with address logic Shunt regulator allows operation with high voltage supplies 0V to 5V input range with single 5V power supply Remote operation with serial digital data link TTL/MOS input/output compatible 0.3× standard width, 8-, 14- or 20-pin DIP package 20 Pin Molded Chip Carrier Package (ADC0838 only) Surface-Mount Package
Interface Overview• CS: Chip select, low level enable. • CH0: Analog input channel 0, or used as IN+/-. • CH1: Analog input channel 1, or used as IN+/-. • GND: Ground. • DI: Data input, channel selection. • DO: Data output, converted data output. • CLK: Chip clock input. • Vcc/REF: Power supply / Reference voltage input. Principle of ADC0832Normally, ADC0832 interface with MCU by 4 lines, CS, CLK, DO and DI, but the DI and DO lines can be tied together and controlled through a bidirectional processor I/O bit with one wire. When ADC0832 is not converting, CS must be pulled high, and the level on CLK, DO, DI is not defined. A conversion is initiated by first pulling the CS line low. This line must be held low for the entire conversion. A clock should then be generated by the processor (if not provided continuously) and output to the A/D clock input, CLK. On each rising edge of the clock the status of the data in (DI) line is clocked into the MUX address shift register. The start bit is the first logic “1” that appears on this line (all leading zeros are ignored). Following the start bit the converter expects the next 2 to 4 bits to be the MUX assignment word. When the start bit has been shifted into the start location of the MUX register, the input channel has been assigned and a conversion is about to begin. An interval of 1⁄2 clock period (where nothing happens) is automatically inserted to allow the selected MUX channel to settle. The SAR status line goes high at this time to signal that a conversion is now in progress and the DI line is disabled (it no longer accepts data). The data out (DO) line now comes out of tri-state and provides a leading zero for this one clock period of MUX settling time. When the conversion begins, the output of the SAR comparator, which indicates whether the analog input is greater than (high) or less than (low) each successive voltage from the internal resistor ladder, appears at the DO line on each falling edge of the clock. This data is the result of the conversion being shifted out (with the MSB coming first) and can be read by the processor immediately. After 8 clock periods the conversion is completed. The SAR status line returns low to indicate this 1⁄2 clock cycle later. If the programmer prefers, the data can be provided in an LSB first format [this makes use of the shift enable (SE) control line]. All 8 bits of the result are stored in an output shift register. On devices which do not include the SE control line, the data, LSB first, is automatically shifted out the DO line, after the MSB first data stream. The DO line then goes low and stays low until CS is returned high. On the ADC0838 the SE line is brought out and if held high, the value of the LSB remains valid on the DO line. When SE is forced low, the data is then clocked out LSB first. All internal registers are cleared when the CS line is high. If another conversion is desired, CS must make a high to low transition followed by address information ADC0832 Timing Diagram
Software and Hardware Design with ADC0832After learned the fundamental principle of analog to digital converter, we can experiment with the ADC0832. The voltage sampled on channel 1 will be displayed on LED display. Toggle on the function select to ‘0832’ before this experiment.
Schematic Diagram
Program Flow Chart
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